The present invention generally relates to logic circuits, and more particularly to a logic circuit building block, herein termed an M Circuit, and the development of subsystems and systems with such M Circuit.
Various types of logic circuit building blocks have been developed by the electronic industry for use in designing systems which operate on two level binary data. One basic building block is the set-reset flip flop. The set-reset flip flop, however, is generally characterized by a truth table in which, for some conditions of data input and data change at the two inputs, the two outputs lose complementation and provide the logic fallacy of identical binary outputs. This is an undesirable condition if complementation is required by the system design. Another undesirable condition occurring in the set-reset flip flop is known as the indeterminate state wherein a particular data transition at the two inputs produce outputs which are unpredictable. Both of these conditions referred to above, that is, loss of complementation and the indeterminate state, arise because two inputs may be simultaneously applied to the set-reset flip flop which cause both of its outputs to be identical. Attempts to overcome these problems have involved the use of clocking, gate logic circuitry in conjunction with one or more set-reset flip flops. This makes the flip flop more complex and also requires, in large systems, clock generators of high power output. This is true since clocking is accomplished at each stage within the system. Similarly, system resetting can also require a large number of wire runs and a large drive capability since, generally, each flip flop or groups of flip flops within a system must be individually reset. The use of a clock also results in a certain slowing down of the system. That is, the maximum speed of operations within the system is affected by the clock rate. Normally, operations are performed on only either the leading or trailing edges of clock pulses. The result, very often, is that the logic elements in the system are not utilized to the fullest extent possible in regard to their inherent speed.
Some of these problems become particularly noticeable when it is desired to separate large quantities of data. If such data separation is attempted using set-reset flip flops, the designer runs into the problem of having a situation involving the loss of complementation at the flip flop output, as discussed above. In addition, the designer must provide a large number of individual resets to the flip flops in the data separation system. On the other hand, where a clock type of flip flop is employed, there must be supplied additional amounts of clock power to accommodate the added gates and flip flop stages.
Thus, it can be seen that there exists a need for a basic building block which can be used to design information generating and processing systems and avoid problems associated with clocking at each stage of data processing. In addition, it would improve the efficiency of such a system if it responded to both the leading and trailing edges of pulses and thereby not have to wait a full cycle to perform each sequential operation. Also, the basic building block employed should not have the inherent characteristics of the set-reset flip flop which permits the loss of complementation at the outputs, and an indeterminate state, but should have its simplicity of design. Furthermore, it would be desirable to have a building block which can easily be reset when combined with other such circuits.